We are seeking an Analog Designer With 5+ Year Of Experience In 16+bit SAR ADC to become an integral part of our team
Responsibilities:
Define the ADC architecture based on Capacitive DAC
Implement calibration loop for the DAC
Simulate all the components (blocks and top level), layout critical blocks
Run DRC, LVS, PEX
Tape out and follow up at TSMC
Test bench qualification, Datasheet writing
Understanding production constrains and ATE​Qualifications:
15+ years of experience in analog circuit
5+ years of experience in 16+ bit SAR ADC
Tools: CADENCE front-end and back-end, Mentor-Siemens simulation and layout verification
Linux based Design
Plus: proficient with at least 1 scripting language Contact: email